Interrupt Feedback

When the Z80 acknowledges an interrupt, it reads 8 bits of data from the data bus. It then uses this data as an instruction or an address. In the Bally Arcade, this data is determined by the contents of the interrupt feedback register (output port $D). In response to a screen interrupt, the contents of the interrupt feedback register are placed directly on the data bus. In response to a light pen interrupt, the lower four bits of the data bus are set to 0 and the upper four bits are the same as the corresponding bits of the feedback register.

[NM:92]

The Vertical Blank Register (output port $A) contains the line number where vertical blanking will begin. The register must be set to 101 or less. Bit 0 should be set to 0 and the line number should be in bits 1–7. The background color will display from the vertical blank line to the bottom of the screen. This allows the screen RAM that would normally be displayed in that area to be used for scratchpad. If the vertical blank register is set to 0, the entire RAM can be used for scratchpad.

[NM:90]

“The vertical blank register contains the line number at which pixel data from the display RAM is no longer used to define the pixels displayed on the screen and has the same address as the vertical blank register of the data chip but is utilized for a different purpose.”

[Patent US4301503]

In order for the Z80 to accept an interrupt, the internal interrupt enable flip-flop must be set by an EI instruction, and one or two of the external interrupt enable bits must be set (output port $E). If bit 1 is set, light pen interrupts can occur. If bit 3 is set, screen interrupts can occur. If both bits are set, both interrupts can occur, and the screen interrupt has higher priority.

The interrupt mode bits determine what happens if an interrupt occurs when the Z80's interrupt enable flip-flop is not set. Each of the two interrupts may have a different mode. In mode 0, the Z80 will continue to be interrupted until it finally enables interrupts and acknowledges the interrupt. In mode 1, the interrupt will be discarded if it is not acknowledged by the next instruction after it occurred. If mode 1 is used, the software must be designed such that the system will not be executing certain Z80 instructions when the interrupt occurs. The opcodes of these instructions begin with CBH, DDH, EDH, and FDH.

The screen interrupt synchronizes the software with the video system. If the screen interrupt is enabled, the CPU will be interrupted when the display completes scanning the line which is contained in the interrupt line register (output port $F). To do so, bit 0 is set to 0 and the line number is sent to bits 1–7.

If the screen interrupt enable bit is set, the Z80 will be interrupted when the video system completes scanning the line in the interrupt register. This interrupt can be used for timing since each line is scanned 60 times a second. It can also be used in conjunction with the color registers to make as many as 256 color-intensity combinations appear on a screen at the same time. Thus, after a screen interrupt, the data within the 8 color registers which can define 8 different color-intensity combinations may be changed to 8 additional color-intensity combinations with the interrupt line register contents also being changed to a subsequent line number. When this line is reached the process may be repeated until the full 256 possible combinations represented by the 5 color bits and 3 intensity bits in each color register have been displayed.

[Patent US4301503]

The light pen interrupt occurs when the light pen trigger is pressed and the video scan crosses the point on the screen where the light pen registers. The interrupt routine can read two registers to determine the position of the light pen. The line number is read from the vertical feedback register (input port $E). Bit 0 is ignored and bits 1–7 indicates the line number. The horizontal position of the light pen can be determined by reading input port $F and subtracting 8. The resultant value is the pixel number, 0 to 159.

[NM:92-3]