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Input/Output Ports
Port Number (hex) | Input | Function | Output | Function |
---|---|---|---|---|
0 | COL0R | Color Register 0 (Right) | ||
1 | COL1R | Color Register 1 | ||
2 | COL2R | Color Register 2 | ||
3 | COL3R | Color Register 3 | ||
4 | COL0L | Color Register 0 (Left) | ||
5 | COL1L | Color Register 1 | ||
6 | COL2L | Color Register 2 | ||
7 | COL3L | Color Register 3 | ||
8 | CONCM | Consumer/Commercial mode | INTST | Intercept Status Feedback |
9 | HORCB | Horizontal Color Boundary, BG Color | ||
A | VERBL | Vertical Blank Register | ||
B | COLBX | Color Block Transfer | ||
C | MAGIC | Magic Register | ||
D | INFBK | Interrupt Feedback | ||
E | INMOD | Interrupt Enable and Mode | VERAF | Vertical Address Feedback |
F | INLIN | Interrupt Line | HORAF | Horizontal Address Feedback |
10 | TONMO | Tone Master Oscillator | SW0 | Player 1 Control Handle |
11 | TONEA | Tone A Frequency | SW1 | Player 2 Control Handle |
12 | TONEB | Tone B Frequency | SW2 | Player 3 Control Handle |
13 | TONEC | Tone C Frequency | SW3 | Player 4 Control Handle |
14 | VIBRA | Vibrato/Tremolo | KEY0 | Keypad Column 0 (right) |
15 | VOLAB | Tone C Volume, Noise Modulation Control | KEY1 | Keypad Column 1 |
16 | VOLC | Tone A Volume, Tone B Volume | KEY2 | Keypad Column 2 |
17 | VOLN | Noise Volume | KEY3 | Keypad Column 3 (left) |
18 | SNDBX | Sound Block Transfer | ||
19 | XPAND | Expander Pixel Definition | ||
1C | POT0 | Player 0 Pot | ||
1D | POT1 | Player 1 Pot | ||
1E | POT2 | Player 2 Pot | ||
1F | POT3 | Player 3 Pot |
Port Descriptions
Currently incomplete
CONCM ($8)
Select video mode (0 = low res 160×102, 1 = high res 320×204).
VERBL ($A)
Vertical Blank. The Address chip needs this register to determine the scan line below which Screen Refresh is no longer needed. The Data chip must duplicate this register to determine when to turn on the border color.
INMOD ($E)
Interrupt Enable and Mode/Vertical Line Feedback. On write, this register enables interrupts and determines the interrupt mode of each. On read, this register contains the vertical line number that a Light Pen Interrupt was received on. Bit 3 of the Interrupt Enable port (0x0E) when set enables line interrupts, while bit 1 of the same register enables the Light Pen interrupt.
INLIN ($F)
Interrupt Line/Horizontal Address Feedback. On write, this register sets the scan line number on which to generate a line interrupt back to the Z80. On read, this register contains the horizontal address (i.e., position in the line) that a Light Pen Interrupt was received on.
[NM:106, 143, source listing 5] Reference: Wizard of Wor arcade disassembly